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TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 1 post office box 655303 ? dallas, texas 75265 complies with itu g.992.2 standard 14-bit integrated a/d and d/a converters 1.104 msps update rate for the rx channel 276 ksps update rate for the tx channel minimum 50 db missing tone rejection for dmt signals integrated tx/rx filters integrated digital phase lock loop (dpll) and vcxo dac integrated equalizer for receive channel integrated pga in receive, and paa in transmit channels direct single serial interface to ti's c54x or c6x dsp (data and control) eight general-purpose i/o pins software and hardware power-down modes industrial temperature range (40 c to 85 c) integrated auxiliary amplifiers for system flexibility single 3.3 v supply 80-pin lqfp (pn) package 2s complement data format description the TLFD500PN is a high-speed analog front end for a remote terminal-side adsl g.lite modem. the device is designed to perform transmit encoding (d/a conversion), receive decoding (a/d conversion), transmit and receive filtering functions, and receive equalizer functions for a frequency division multiplex (fdm) g.lite application. the receive channel has an update rate of 1.104 msps, while the transmit channel has an update rate of 276 ksps. both channels use 2s complement data format. when used in a g.lite system, the TLFD500PN requires a minimum number of external components. the device incorporates integrated filtering, dpll, vcxo dac (uses 2s complement data format), and 8 general-purpose i/o ports. the general-purpose i/o ports provide a means of reading or writing status bits in the system. four auxiliary amplifiers on the chip can be configured (external components may be required) to provide additional onboard filtering and amplification. a simple serial interface for data transfer on the digital side reduces system component count. the interface can be connected directly to the ti c6x and c54x families of dsps. the TLFD500PN device is available in an 80-pin pn lqfp package. copyright ? 1999, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 2 post office box 655303 ? dallas, texas 75265 23 dvss dvdd reset mclkin/pllclkin nc dgpo dvss dvss_io dvdd_io dvdd gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 fsx fsr 40 39 38 37 36 35 34 33 32 31 30 29 27 27 26 25 24 23 22 21 4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 amp4outp amp4outm nc amp3outp amp3inm amp3inp amp3outm avdd_rx avss_rx rxinp rxinm hpf2outp hpf2inm hpf2inp hpf2outm hpf1outp hpf1inm hpf1inp hpf1outm vss 5678 pn package (top view) vmid_rx 59 58 57 56 55 60 54 nc dvss_rx dvss_rx dvss_rx dvss_rx nc dvss_rx amp1inp vcxocntl amp2inm amp2outp txoutp txoutm avdd_tx avss_tx amp1outp 52 51 50 53 9 10 11 12 13 49 48 1 amp2outm avdd_rx 47 46 45 44 14 15 16 17 txbandgap compdac2 compdac1 pwrdn avdd_ref refp refm avss_ref amp4inm amp4inp sdx sclk 18 19 20 rxbandgap pllsel 43 42 41 dvdd_rx avss_rx dvss amp1inm amp2inp amp1outm sdr nc no connection TLFD500PN
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 3 post office box 655303 ? dallas, texas 75265 functional block diagram mclkin serial interface and control general purpose i/o digital hpf digital lpf tx dac tx lpf rx lpf equalizer+ rx lpf hpf2 hpf1 internal reference clock generator vcxo dac external vcxo paa sclk sdx sdr fsx fsr txoutp/ txoutm rxinp/ rxinm hpf2outp/ hpf2outm hpf2inp/ hpf2inm ampoutp/ ampoutm hpf1outp/ hpf1outm hpf1inp/ hpf1inm ampinp/ ampinm txbandgap/ rxbandgap refm refp vmid_rx vcxocntl 30 khz to 138 khz 30 khz 138 khz aux amps(4) gpi00gpi07 138 khz 14 bit 4.416 msps 552 khz 0 to 24 db (1 db/step) tx paa 14 bit 4.416 msps 552 khz 0 to 9 db (0.25 db/step) rx pga3 0 to 18 db (6 db/step) rx pga2 180 khz 0 to 12 db (3 db/step) rx pga1 180 khz 35.328 mhz adc analog loop-back pga pga pga digital loop-back 276 ksps 1104 ksps dpll internal clock external oscillator 35.328 mhz mclkin see note see note note: refer to figure 17 for application details.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description amp1inp amp4inp 11,2,66,59 i auxiliary amplifier 14 positive input amp1inm amp4inm 10,3,65,60 i auxiliary amplifier 14 negative input amp1outp amp2outp 9,4 o auxiliary amplifier 12 positive output. outputs are self-biased to avdd_tx/2. amp3outp amp4outp 64, 61 o auxiliary amplifier 34 positive output. outputs are self-biased to avdd_rx/2. amp1outm amp2outm 12,1 o auxiliary amplifier 12 negative output. outputs are self-biased to avdd_tx/2. amp3outm amp4outm 67,62 o auxiliary amplifier 34 negative output. outputs are self-biased to avdd_rx/2. avdd_ref 47 i analog supply for reference circuit avdd_rx 48,68 i rx channel analog supply avdd_tx 7 i tx channel analog supply avss_ref 44 i analog supply return for reference(analog ground) avss_rx 49,69 i rx channel analog supply return (analog ground) avss_tx 8 i tx channel analog supply return (analog ground) compdac1 16 i tx channel decoupling cap input a. add 1 m f capacitor to avdd_tx compdac2 15 i tx channel decoupling cap input b. add 1 m f capacitor to avdd_tx dgpo 35 o direct general-purpose output. this pin reflects the last value written to the dgpo bit location in the sdr data stream. it is a general-purpose output that does not require a secondary transfer to control. dvdd 31,39 i digital power supply dvdd_io 32 i digital i/o buffer supply dvdd_rx 51 i rx channel digital supply dvss 34,40,41 i digital ground dvss_io 33 i digital i/o buffer supply return (digital ground) dvss_rx 52,54,55, 56,57 i rx channel digital supply return (digital ground) fsx 22 o serial port frame sync transmit signal fsr 21 o serial port frame sync receive signal gpio0gpio7 2330 i/o general-purpose i/o hpf1inp 78 i rx channel stage 1 amplifier positive input. input signal needs to have avdd_rx/2 common mode voltage. hpf1inm 77 i rx channel stage 1 amplifier negative input. input signal needs to have avdd_rx/2 common mode voltage. hpf2inp 74 i rx channel stage 2 positive input. input signal need to have avdd_rx/2 common mode voltage. hpf2inm 73 i rx channel stage 2 negative input. input signal need to have avdd_rx/2 common mode voltage. hpf1outp 76 o rx channel stage 1 amplifier positive output. used to connect external components to obtain stage 1 hpf. hpf1outm 79 o rx channel stage 1 amplifier negative output. used to connect external components to obtain stage 1 hpf. hpf2outp 72 o rx channel stage 2 positive output. output signal has avdd_rx/2 common mode voltage. hpf2outm 75 o rx channel stage 2 negative output. output signal has avdd_rx/2 common mode voltage. mclkin/pllclkin 37 i multiplexed pin based on value of pllsel. selects master clock input, or clock input for pll mode.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 5 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal i/o description name no. i/o description nc 36,53, 58, 63 no connection. keep floating. pllsel 42 i selects between vcxo mode and dpll mode. if the pin is tied high pll mode is selected. pin should be tied low for vcxo mode. cannot be left floating. pwrdn 17 i power-down pin. when pwrdn is pulled low the device goes into power-down mode. the default state of this pin is low. refm 45 o negative reference filter node. this terminal is provided for low-pass filtering of the internal band-gap reference. the optimal ceramic capacitor value is 10 m f (tantalum) and 0.1 m f (ceramic), connected to analog ground. the nominal dc voltage at this terminal is 0.5 v. refp 46 o positive reference filter node. this terminal is provided for low-pass filtering of the internal band-gap reference. the optimal ceramic capacitor value is 10 m f (tantalum) 0.1 m f (ceramic), connected to analog ground. the nominal dc voltage at this terminal is 2.5 v. reset 38 i device reset input pin. initializes all the device's internal registers to their default values. the default state of this pin is low. rxbandgap 43 o rx channel band-gap filter node. this terminal is provided for decoupling of the 1.5-v band-gap reference. the optimal capacitor value is 10 m f (tantalum) and 0.1 m f (ceramic). this node should not be used as a voltage source. rxinp 70 i rx channel stage 3 positive input. the input is self-biased at avdd_rx/2. rxinm 71 i rx channel stage 3 negative input. the input is self-biased at avdd_rx/2. sclk 19 o serial port shift clock (transmit and receive) sdr 20 i serial data receive from dsp sdx 18 o serial data transmit to dsp txbandgap 14 o tx channel band-gap filter node. this terminal is provided for decoupling of the 1.5-v band-gap reference. the optimal capacitor value is 10 m f (tantalum) and 0.1 m f (ceramic). this node should not be used as a voltage source. txoutp 5 o tx channel positive output txoutm 6 o tx channel negative output vcxocntl 13 o dac output to control onboard vcxo vmid_rx 50 i/o decoupling vmid for adc. add 10 m f (tantalum) and 0.1 m f (ceramic) capacitors to analog ground. vss 80 i substrate. connect to analog ground. detailed description transmit the transmit channel is powered by a high performance dac. the transmit channel update rate is 276 khz. the dac is a 14-bit dac at 4.416-mhz. this provides 16x oversampling. a band-pass filter limits the output of the transmitter to a frequency range of 30 khz to 138 khz. a differential amplifier drives the output into the external line driver. the differential amplifier has programmable attenuation for added flexibility. the transmitter high-pass filter can be bypassed by writing the appropriate bit to the filter bypass control register (bcr). the output spectrum of the dac complies with the nonoverlapped power spectrum density (psd) mask specified in the itu draft recommendation g.992.2 for g.lite. the txpaa is a programmable-attenuation amplifier. it provides 0 db to 24 db of attenuation in1-db steps. the txpaa is controlled via the paa control register (pcr). for details about register programming see the register programming section.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 6 post office box 655303 ? dallas, texas 75265 detailed description (continued) receive the receive channel consists of a high-pass filter, a programmable gain amplifier, an adc, and filters. in addition, it has an equalizer to attain maximum system performance. the input of the receiver is fully differential. the adc in the receive channel is a 14-bit converter which samples at 4.416 msps for 4x oversampling. an on-chip decimator reduces the sampling frequency to 1.104 mhz. the low pass filtering of the receive channel limits the converted data to frequencies below 552 khz. the high-pass analog filter is used to reject the near-end echo to maximize the dynamic range of the adc. the high-pass filter consists of two stages: (1) a second order high-pass filter (hpf1) and, (2) a third order elliptic high-pass filter (hpf2). both stages have a cutoff at 180 khz. the filter is divided into two stages to minimize the noise from a single stage being amplified throughout. together, the two high-pass filters typically attenuate the echo power by 30 db. there is a programmable gain amplifier (pga) between the two filters for coarse gain adjustments of 0-db 12-db in 3-db steps. after the high-pass filter stage, the receiver channel has a 0-db 18-db pga that can be adjusted in 6-db steps. hpf2 and pgas are integrated in one block. figure 1(a), 1(b), and 1(c) show the frequency response of hpf1 and hpf2 (with pgas). the pga is followed by a 552-khz low-pass filter with a programmable 25-db/mhz slope (5-db/mhz step) equalizer incorporated. after the equalizer, there is a fine-gain adjustment pga of 0-db to 9-db in 0.25-db steps. all the rx pgas are controlled via the pga control registers (pcrrx1 and pcrrx2). see the register programming section for details about register programming.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 7 post office box 655303 ? dallas, texas 75265 detailed description (continued) 100 150 200 250 0 0.5 1 gain db 50 0 f frequency hz 50 1.5 2 10 5 4 6 8 10 1 1.2 1.4 gain db 2 0 f frequency hz 2 1.6 1.8 2 10 5 (a) rx-stage hpf1 frequency response (0 to 200 khz) (b) rx-stage hpf1 frequency response (100 khz to 200 khz) khz 38.6 90.6 142. 6 194. 6 246. 6 298. 6 27 24 21 18 15 12 9 6 3 0 db (c) rx-stage hpf2 frequency response (pga1 = pga2 = 0 db) figure 1. rx stage hpf1 and hpf2 frequency response clock control vcxo mode the vcxodac uses a 12-bit, 2s complement number to control a 0-v to 3-v analog output. the two 8-bit registers, vcr-m and vcr-l, are used to generate the 12-bit control code (2s complement). this implies the use of 16 bits to obtain a 12-bit number. vcr-m register occupy the most significant 8 bits in the 12-bit number and the lower 4 bits of the vcr-l register (vcr-l[3:0] ) are used for the low 4 bits of the 12-bit number. the 12-bit code is updated every time either register is updated. vcr-l[7:4] must always be zero.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 8 post office box 655303 ? dallas, texas 75265 clock control dpll mode as an alternative to the vcxodac and vcxo, an off-chip crystal oscillator (xo) followed by an on-chip digital pll are also implemented. refer to figure 7 for an internal function block diagram. the input clock (35.328 mhz) goes to a programmable frequency divider to generate sampling clock for the adc and dac converters. by changing the divide ratio, the phase of the sampling clock can be adjusted. setting pllsel (pin 42) high will enable the dpll mode. refer to dpll section for detail. clock generation the clock generation block creates the necessary internal and external clocks needed by the device. all the clocks generated are produced from the clkin signal. the following are recommended operational parameters for the external vcxo: 3.3-v supply, 35.328 mhz 50 ppm center frequency, and input control voltage range of 0 v3 v. the recommended duty cycle is 50/50. clock generation sclk sclk is an output and is used for serial data transfer. it runs at 35.328 mhz. although sclk and mclk run at the same speed, there is no fixed phase relationship between them. serial interface the serial interface on the TLFD500PN connects directly to ti's c54x or c6x families of dsps. the interface operates at 35.328 mhz. the serial port consists of five signals: sclk, fsx, fsr, sdx, and sdr. a typical connection diagram is shown in figure 2. dsp sclk clkr clkx fsx fsr dx dr fsr fsx sdr sdx TLFD500PN figure 2. typical serial port connection the serial port utilizes a primary/secondary scheme to transfer conversion data and control register data. a primary transfer scheme, used to transfer conversion data, occurs every conversion period. a secondary transfer scheme, used to transfer control data, happens only when requested by the host processor. the host processor requests a secondary transfer by using the lsb of the sdr data of the primary scheme. a value of 1 indicates a secondary transfer request. once the secondary request is made and the primary transfer has been completed, secondary frame sync pulse (fsx/fsr) are transmitted to the host processor to indicate the beginning of the secondary transfer. the secondary fsx signal arrives 16 sclks after the primary fsx, and thus 48 sclks after the host processor request. this is because the span between fsx pulses for primary transfers is always 32 sclks. each bit is read/written at the rising edge of the sclk clock. data bit mappings and example data transfers are shown in table 1.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 9 post office box 655303 ? dallas, texas 75265 detailed description (continued) table 1. sdr lsb control function control bit d0 control bit function 0 no secondary transfer requested 1 secondary transfer requested primary transfer data mapping the data bit mapping of a primary transfer is shown in figure 3. bits d2d15 of the sdr data stream are dac data. d1 is the control bit for the dgpo pin. the value written to this bit is reflected on the dgpo pin. see the timing diagram in figures 5 and 6 for detailed timing information. d0 is the secondary transfer request bit. when a 1 is written to this bit, the host is requesting a secondary data transfer. in the sdx data stream, d2d15 contain the adc conversion data. d0 and d1 can be set to reflect the values of gpio1 and gpio2. to set d0 and d1 to reflect the gpio values, the proper bit in the mcr register needs to be set. sdr sdx d15 d2 data to codec data from codec dgpo bit secondary transfer request gpio1 gpio0 gpiox status if configured as input. zero if gpiox configured as output or if masked off d1 d0 d15 d2 figure 3. primary transfer data bit mapping secondary transfer data mapping secondary serial communication is used to configure the device. the data bit mapping for a secondary transfer is shown in figure 4. bits d10d14 of the sdr data from the host contain the address of the control register involved in the transfer. d15 is a r/w bit. to read out the control register by the host processor, bit r/w must be set to 1. to write to the control register by the host processor, bit r/w must be set to 0. during a read operation, bits d0d7 are don't care. for a write operation, bits d0d7 contain the data for the register addressed by d10d14. the eight bits of sdx always reflect the status of gpi007. if the secondary transfer is a read operation, the contents of the control register addressed by d10d14 of the sdr data are reflected in bits d0d7 of the sdx data stream. if the secondary transfer is a write operation, bits d0d7 on sdx will be all zeroes.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 10 post office box 655303 ? dallas, texas 75265 secondary transfer data mapping (continued) sdr (read) d15 don't care gpio0 7 status d9 d0 d9 d8 d7 1 a4 a3 a2 a1 a0 sdr (write) sdx (read) sdx (write) register address don't care 0 a4 a3 a2 a1 a0 d8 d7 d15 d0 d8 d7 register data read cycle (codec register data read by dsp) register address data to the register d0 gpio0 7 status d15 d0 d8 d7 all 0 write cycle (dsp data write to codec register) don't care figure 4. secondary transfer data bit mapping example data transfers figures 5(a) and 5(b) show the timing relationship for sclk, fsx, sdx, fsr, and sdr in a primary communication. the timing sequence for this operation is as follows: 1. fs is set high and remains high during one sclk period, then returns to low. 2. a 16-bit word is transmitted from the adc (sdx), and a 16-bit word is received for dac conversion (sdr). figure 6(a) and 6(b) shows the timing relationship with secondary request.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 11 post office box 655303 ? dallas, texas 75265 detailed description (continued) sclk (output) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fsx (output) sdx (output) t1 t2 t3 t1: dsp detects fsx t2: TLFD500PN sends data t3: dsp latches data (a) TLFD500PN to dsp t1: dsp detects fsr t2: dsp sends data t3: TLFD500PN latches data d15 fsr (output) sdr (input) t1 t2 t3 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (b) dsp to TLFD500PN sclk (output) note: ti dsp requires 10 ns after the positive edge of the sclk to give the sdr data. this plus the board delay, output buffer ( for sclk) and input buffer delay (for sdr) to around 17 ns. as a consequence the sdr data can not be latched at the negative edge of sclk. figure 5. data transfers
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 12 post office box 655303 ? dallas, texas 75265 detailed description (continued) 48 sclks 16 sclks p fsr ?????????????? ?????????????? ?????????????? ??????? ??????? ??????? data command zeroes 128 sclks p p p p p ps s data data data data data data fsx sdr sdx status zeroes zeroes don't care don't care (a) with secondary request (b) without secondary request 32 sclks 16 sclks p fsr ??????????????????????? ??????????????????????? ??????????????????????? data zeroes 128 sclks p p p p p p data data data data data data fsx sdr sdx zeroes zeroes zeroes don't care figure 6. data transfers
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 13 post office box 655303 ? dallas, texas 75265 detailed description (continued) general purpose i/o port (gpio) the general-purpose i/o port provides eight input/output pins and one output-only pin for control of external circuitry, or for reading the status of external devices. the eight input/output pins are labeled gpio0 gpio7. the output-only pin is labeled dgpo (direct general-purpose output). this pin is labeled as direct because a secondary transfer is not required to write to this pin. the gpio pins are controlled and read in the gpr-d register. the gpr-c register is used to configure the gpio pins as input or output pins. the default reset condition is 1 111111 1b, indicating that all are configured as inputs. for further details on register programming see the register programming section. the dgpo pin does not need configuring and is controlled by the d1 bit in the sdr data stream (that is, from the dsp to the TLFD500PN) during primary data transfers. in addition, a secondary transfer is not required to read gpio0 and gpio1 when they are configured as inputs. their values can be mapped into the lower two bits of the sdx data stream (that is, from TLFD500PN to dsp) during primary data transfers. to map the values of gpio0 and gpio1 into the lower two bits of the sdx adc data stream, set the appropriate bit in the mcr register. for more flexibility, the values of gpio0 gpio7 are mapped into the upper eight data bits of the sdx data stream on secondary data transfers. this allows the host processor to read the values of the gpio pins and the contents of another control register during the same secondary data transfer. when a gpio pin is being configured as an output, its corresponding status bit in the sdx data stream will be the last value written to the output pin. each output is capable of driving 2 ma. reference system the integrated reference provides voltage and current to the internal analog blocks. it is also brought out to external pins for noise decoupling. they should not be used as dc voltage source. when the internal reference is being used by the device, the device may be powered down by writing the appropriate reference control bit in the main control register (mcr) to achieve power savings during periods of device inactivity. auxiliary amplifiers four auxiliary high-performance operational amplifiers on the chip allow for additional onboard filtering and amplification with minimal component count. each op-amp has differential inputs and outputs, with 2 input pins and 2 output pins. each op-amp can be enabled by register programming. the typical specifications for the operational amplifiers are as follows: dc gain: 126 db bandwidth: 116 mhz psrr: 100 db at dc, 70 db at 1 mhz, and 40 db at 4 mhz output common-mode: avdd_rx/2 (auxiliary amplifier 3,4) or avdd_tx/2 (auxiliary amplifier 1,2) input interface: ac coupled device power-up sequence all digital and analog supplies must be properly biased. all supply pins are mandatory. the power supply can not be switched, even when the codec has been powered down or parts of the codec are in power-down mode. reset must be held at least 20 m s after power up. to reset the reference circuit and registers requires 100 ms. when the chip is woken up from hardware power-down mode, it takes100 ms to reset the reference circuit before the chip works in normal mode. when the chip is woken up from software power-down mode, only 20 m s is needed before valid data comes out (reference must be kept on). register values will not change in either wake-up operation.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 14 post office box 655303 ? dallas, texas 75265 detailed description (continued) register programming the codec registers are listed in table 2, with each bit of each register defined. all registers are 8-bit wide. note: bits not defined in the table are reserved for future use. during a read, the reserved bit read value is not guaranteed. during a write, only zeroes can be written to reserved bits. table 2. codec registers register name address mode function name a4 a3 a2 a1 a0 bcr 00001 r/w d0: power-down rx hp filter 1 d1: power-down rx hp filter 2 d2: bypass tx digital hp filter d3: echo mode: echo sdr data back to sdx d4: reserved d5: reserved d6: reserved pcr-rx1 00010 r/w d[5:0] = rxpga3[5:0]; fine gain, 0 to 9 db, 0.25-db steps pcr-rx2 00011 r/w d[2:0] = rxpga1[2:0]; 0 to 12db, 3-db steps d[4:3] = rxpga2[1:0]; 0 to 18 db, 6-db steps pcr-tx 00100 r/w d[4:0] = tx paa[4:0]; 0 to 24db, 1-db steps eqr 00101 r/w d[2:0] = eq[2:0] 0 to 25 db, 5 db/mhz steps; d[6:4] = eq_pga[2:0] 0 to 6 db, 1 db steps vcr-m 00110 r/w d[7:0] = vcxo dac control bit[11:4]. vcr-l 00111 r/w d[3:0] = vcxo dac control bit[3:0]. d[7:4] must always be zero. gpr-c 01000 r/w d[7:0] = gpio1 i/o control (0 = output, 1 = input) gpr-d 01001 r/w d[7:0] = gpio data register reserved 01010 r/w for future use. read or write of register not allowed. auxr 01011 r/w d0: enable auxiliary amplifier 2 d1: enable auxiliary amplifier 1 d2: enable auxiliary amplifier 3 d3: enable auxiliary amplifier 4 nco_def 01100 r/w d[7:0] = default nco divide number nco_div_delay 01101 r/w d[7:0] = number of samples, from current secondary transfer, after which effect of delta will occur. nco_delta 01110 r/w d[7:4] = delta from default for first sample of data frame (8 through 7) d[3:0] = number of times nco divider remains changed from default before being set back to default (0 through 15) mcr 01111 r/w d0: s/w power-down main reference d1: s/w power-down tx channel with reference still on d2: s/w power-down rx channel with reference still on d3: s/w power-down vcxo with reference still on d4: s/w reset d5: analog loop back (refer to block diagram) d6: digital loop back (refer to block diagram) d7: enable gpio 1 and 2 to show in sdx primary data
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 15 post office box 655303 ? dallas, texas 75265 bcr bypass control register address: 00001b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved echo txhpen rxhp2pd rxhp1pd table 3. eqr bit definition d7 d6 d5 d4 d3 d2 d1 d0 reg. value bit name description r reserved bit reserved for future use r reserved bit reserved for future use r reserved bit reserved for future use r reserved bit reserved for future use 0 echo do not echo sdr data on sdx 1 0x08 echo echo sdr data on sdx (see note 1) 0 txhpen enable tx hp filter 1 0x04 txhpen bypass tx hp filter 0 rxhp2pd power up rx hp filter 2 1 0x02 rxhp2pd power down rx hp filter 2 0 rxhp1pd power up rx hp filter 1 1 0x01 rxhp1pd power down rx hp filter 1 note 1: echo mode allows for a quick verification of the serial interface operation. it sends back the data from input data buff er to the output data buffer and does not exercise the rx or tx channel.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 16 post office box 655303 ? dallas, texas 75265 pcr-rx1 programmable gain control register 1 for rx channel pga3 address: 00010b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved rxpga3[5] rxpga3[4] rxpga3[3] rxpga3[2] rxpga3[1] rxpga3[0] table 4. pcr-rx1 gain d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description r reserved bit reserved for future use r reserved bit reserved for future use 0 0 0 0 0 0 0x00 rxpga3[5:0] 0db 0 0 0 0 0 1 0x01 0.25db 0 0 0 0 1 0 0x02 0.50db 0 0 0 0 1 1 0x03 0.75db 0 0 0 1 0 0 0x04 1.00db 0 0 0 1 0 1 0x05 1.25db 0 0 0 1 1 0 0x06 1.50db 0 0 0 1 1 1 0x07 1.75db 0 0 1 0 0 0 0x08 2.00db 0 0 1 0 0 1 0x09 2.25db 0 0 1 0 1 0 0x0a 2.50db 0 0 1 0 1 1 0x0b 2.75db 0 0 1 1 0 0 0x0c 3.00db 0 0 1 1 0 1 0x0d 3.25db 0 0 1 1 1 0 0x0e 3.50db 0 0 1 1 1 1 0x0f 3.75db 0 1 0 0 0 0 0x10 4.00db 0 1 0 0 0 1 0x11 4.25db 0 1 0 0 1 0 0x12 4.50db 0 1 0 0 1 1 0x13 4.75db 0 1 0 1 0 0 0x14 5.00db 0 1 0 1 0 1 0x15 5.25db 0 1 0 1 1 0 0x16 5.50db 0 1 0 1 1 1 0x17 5.75db 0 1 1 0 0 0 0x18 6.00db 0 1 1 0 0 1 0x19 6.25db 0 1 1 0 1 0 0x1a 6.50db 0 1 1 0 1 1 0x1b 6.75db 0 1 1 1 0 0 0x1c 7.00db 0 1 1 1 0 1 0x1d 7.25db 0 1 1 1 1 0 0x1e 7.50db 0 1 1 1 1 1 0x1f 7.75db 1 0 0 0 0 0 0x20 8.00db 1 0 0 0 1 1 0x21 8.25db 1 0 0 1 0 0 0x22 8.50db
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 17 post office box 655303 ? dallas, texas 75265 table 4. pcr-rx1 gain (continued) d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description 1 0 0 0 1 1 0x23 rxpga3[5:0] 8.75db 1 0 0 1 0 0 0x24 9.00db 1 0 0 1 0 1 0x25 invalid 1 0 0 1 1 0 0x26 invalid 1 0 0 1 1 1 0x27 invalid 1 0 1 0 0 0 0x28 invalid 1 0 1 0 0 1 0x29 invalid 1 0 1 0 1 0 0x2a invalid 1 0 1 0 1 1 0x2b invalid 1 0 1 1 0 0 0x2c invalid 1 0 1 1 0 1 0x2d invalid 1 0 1 1 1 0 0x2e invalid 1 0 1 1 1 1 0x2f invalid 1 1 0 0 0 0 0x30 invalid 1 1 0 0 0 1 0x31 invalid 1 1 0 0 1 0 0x32 invalid 1 1 0 0 1 1 0x33 invalid 1 1 0 1 0 0 0x34 invalid 1 1 0 1 0 1 0x35 invalid 1 1 0 1 1 0 0x36 invalid 1 1 0 1 1 1 0x37 invalid 1 1 1 0 0 0 0x38 invalid 1 1 1 0 0 1 0x39 invalid 1 1 1 0 1 0 0x3a invalid 1 1 1 0 1 1 0x3b invalid 1 1 1 1 0 0 0x3c invalid 1 1 1 1 0 1 0x3d invalid 1 1 1 1 1 0 0x3e invalid 1 1 1 1 1 1 0x3f invalid note 2: the formula to convert bit value to rxpga3 gain in db is rxpga3 gain (in db) = rxpga3[5:0] (in decimal) x 0.25db similarly one can compute the rxpga3 [5:0] bit combination needed, given the gain in db. caution: performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. the user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 18 post office box 655303 ? dallas, texas 75265 pcr-rx2 programmable gain control register 2 for rx channel pga1 and pga2 address: 00011b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved rxpga2[1] rxpga2[0] rxpga1[2] rxpga1[1] rxpga1[0] table 5. pcr-rx2 gain d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description r reserved bit reserved for future use r reserved bit reserved for future use r reserved bit reserved for future use 0 0 0x00 rxpga2[1:0] 0db 0 1 0x08 6db 1 0 0x10 12db 1 1 0x18 18db 0 0 0 0x00 rxpga1[2:0] 0db 0 0 1 0x01 3db 0 1 0 0x02 6db 0 1 1 0x03 9db 1 0 0 0x04 12db 1 0 1 0x05 invalid 1 1 0 0x06 invalid 1 1 1 0x07 invalid notes: 3. the formula to convert bit value to rxpga2 gain in db is rxpga2 gain (in db) = rxpga2[1:0] (in decimal) x 6db similarly the needed rxpga2[1:0] bit combination can be computed, given the gain in db. 4. the formula to convert bit value to rxpga1 gain in db is rxpga1 gain (in db) = rxpga1[2:0] (in decimal) x 3db similarly the needed rxpga1[2:0] bit combination can be computed, given the gain in db. caution: performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. the user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination. pcr-tx programmable attenuation control register for tx channel address: 00100b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved txpaa[4] txpaa[3] txpaa[2] txpaa[1] txpaa[0]
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 19 post office box 655303 ? dallas, texas 75265 pcr-tx programmable attenuation control register for tx channel (continued) table 6. pcr-tx attenuation d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description r reserved bit reserved for future use r reserved bit reserved for future use r reserved bit reserved for future use 0 0 0 0 0 0x00 txpaa[4:0] 0 db 0 0 0 0 1 0x01 1 db 0 0 0 1 0 0x02 2 db 0 0 0 1 1 0x03 3 db 0 0 1 0 0 0x04 4 db 0 0 1 0 1 0x05 5 db 0 0 1 1 0 0x06 6 db 0 0 1 1 1 0x07 7 db 0 1 0 0 0 0x08 8 db 0 1 0 0 1 0x09 9 db 0 1 0 1 0 0x0a 10 db 0 1 0 1 1 0x0b 11 db 0 1 1 0 0 0x0c 12 db 0 1 1 0 1 0x0d 13 db 0 1 1 1 0 0x0e 14 db 0 1 1 1 1 0x0f 15 db 1 0 0 0 0 0x10 16 db 1 0 0 0 1 0x11 17 db 1 0 0 1 0 0x12 18 db 1 0 0 1 1 0x13 19 db 1 0 1 0 0 0x14 20 db 1 0 1 0 1 0x15 21 db 1 0 1 1 0 0x16 22 db 1 0 1 1 1 0x17 23 db 1 1 0 0 0 0x18 24 db 1 1 0 0 1 0x19 invalid 1 1 0 1 0 0x1a invalid 1 1 0 1 1 0x1b invalid 1 1 1 0 0 0x1c invalid 1 1 1 0 1 0x1d invalid 1 1 1 1 0 0x1e invalid 1 1 1 1 1 0x1f invalid note 5: the formula to convert bit value to txpaa attenuation in db is txpaa attenuation (in db) = txpaa[4:0] (in decimal) x (1)db similarly one can compute the txpaa[4:0] bit combination needed, given the attenuation in db. caution: performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. the user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 20 post office box 655303 ? dallas, texas 75265 eqr equalizer slope and gain control register address: 00101b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved eqpga[2] eqpga[1] eqpga[0] reserved eq[2] eq[1] eq[0] table 7. eqr slope and gain d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description r reserved bit reserved for future use 0 0 0 0x00 eqpga[2:0] 0db 0 0 1 0x10 1db 0 1 0 0x20 2db 0 1 1 0x30 3db 1 0 0 0x40 4db 1 0 1 0x50 5db 1 1 0 0x60 6db 1 1 1 0x70 invalid r reserved bit reserved for future use 0 0 0 0x00 eq[2:0] 0db slope 0 0 1 0x01 5db slope 0 1 0 0x02 10db slope 0 1 1 0x03 15db slope 1 0 0 0x04 20db slope 1 0 1 0x05 25db slope 1 1 0 0x06 invalid 1 1 1 0x07 invalid notes: 6. the formula to convert bit value to eqpga gain in db is eqpga gain (in db) = eqpga[2:0] (in decimal) x 1 db similarly one can compute the eqpga[2:0] bit combination needed, given the gain in db. 7. the formula to convert bit value to eq slope in db is eq slope (in db/mhz) =eq[2:0] (in decimal) x 5 db/mhz similarly one can compute the eq[2:0] bit combination needed, given the slope in db/mhz. caution: performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. the user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 21 post office box 655303 ? dallas, texas 75265 vcr-m vcxo dac control register msb address: 00110b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 vcrm[7] vcrm[6] vcrm[5] vcrm[4] vcrm[3] vcrm[2] vcrm[1] vcrm[0] vcr-l vcxo dac control register lsb address: 00111b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 vcrl[3] vcrl[2] vcrl[1] vcrl[0] table 8 shows some representative analog outputs. table 8. representative analog outputs operation hex result analog output comments vcrm[7:0] * 2 4 + vcrl[3:0] 0x800 0 v min scale 0x801 d v just above min 0xfff 2047 d v just below mid 0x000 2048 d v mid scale 0x001 2049 d v just above mid 0x7fe 4094 d v just below max 0x7ff 4095 d v max scale where stepsize, d = (3/4095) v. for example, if 0xaa7 is desired, vcr-m and vcr-l should be set to 0xaa and 0x07; if 0x539 is desired, vcr-m and vcr-l should be set to 0x53 and 0x09.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 22 post office box 655303 ? dallas, texas 75265 gpr-c gpio i/o direction control register address: 01000b contents at reset: 1 1111111b d7 d6 d5 d4 d3 d2 d1 d0 gpioc[7] gpioc[6] gpioc[5] gpioc[4] gpioc[3] gpioc[2] gpioc[1] gpioc[0] table 9. gpr-c direction control d7 d6 d5 d4 d3 d2 d1 d0 reg value bit name description 0 gpioc[7] configure gpio 7 pin as output 1 0x80 gpioc[7] configure gpio 7 pin as input 0 gpioc[6] configure gpio 6 pin as output 1 0x40 gpioc[6] configure gpio 6 pin as input 0 gpioc[5] configure gpio 5 pin as output 1 0x20 gpioc[5] configure gpio 5 pin as input 0 gpioc[4] configure gpio 4 pin as output 1 0x10 gpioc[4] configure gpio 4 pin as input 0 gpioc[3] configure gpio 3 pin as output 1 0x08 gpioc[3] configure gpio 3 pin as input 0 gpioc[2] configure gpio 2 pin as output 1 0x04 gpioc[2] configure gpio 2 pin as input 0 gpioc[1] configure gpio 1 pin as output 1 0x02 gpioc[1] configure gpio 1 pin as input 0 gpioc[0] configure gpio 0 pin as output 1 0x01 gpioc[0] configure gpio 0 pin as input note 8: a particular gpioc control bit configures direction for the corresponding gpiod data bit. gpr-d gpio data register address: 01001b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 gpiod[7] gpiod[6] gpiod[5] gpiod[4] gpiod[3] gpiod[2] gpiod[1] gpiod[0] caution: gpiod[7:0] corresponds to pins gpio7gpio0 respectively.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 23 post office box 655303 ? dallas, texas 75265 auxr auxiliary amplifier enable register address: 01011b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved amp4en amp3en amp1en amp2en table 10. auxiliary amplifier-control d7 d6 d5 d4 d3 d2 d1 d0 reg value bit name description r reserved bit reserved for future use r reserved bit reserved for future use r reserved bit reserved for future use r reserved bit reserved for future use 0 amp4en disable amplifier 4 1 0x08 amp4en enable amplifier 4 0 amp3en disable amplifier 3 1 0x04 amp3en enable amplifier 3 0 amp1en disable amplifier 1 1 0x02 amp1en enable amplifier 1 0 amp2en disable amplifier 2 1 0x01 amp2en enable amplifier 2 caution: performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. the default condition is with the amplifiers switched off. nco_def numerically controlled oscillator default value register address: 01100b contents at reset: 01000000b (64 decimal) d7 d6 d5 d4 d3 d2 d1 d0 reserved ncdef[6] ncdef[5] ncdef[4] ncdef[3] ncdef[2] ncdef[1] ncdef[0] table 11. nco default value table d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description r reserved bit reserved for future use 0 0 0 0 0 0 0 0 00 decimal 0, invalid 0 01 0 2e decimal 1 to 46, invalid 0 1 0 1 1 1 1 0 2f decimal 47, invalid 0 1 1 0 0 0 0 0 30 ncdef[7:0] decimal 48, invalid 0 31 0 5c ncdef[7 : 0] decimal 49 to 92, valid 1 0 1 1 1 0 1 0 5d decimal 93, invalid 1 0 1 1 1 1 0 0 5e decimal 94, invalid 0 5f 0 ff decimal 95 onwards, invalid caution: the sum ncdef[7:0] + ncdel[3:0] should always be between 48 and 93. out-of-bound values should not be used.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 24 post office box 655303 ? dallas, texas 75265 nco_div_delay numerically controlled oscillator delay control register address: 01101b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 ncdly[7] ncdly[6] ncdly[5] ncdly[4] ncdly[3] ncdly[2] ncdly[1] ncdly[0] table 12. nco default value d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description 0 0 0 0 0 0 0 0 0 00 invalid 0 0 0 0 0 0 0 1 0 01 invalid 0 0 0 0 0 0 1 0 0 02 ncdly[7:0] adclk jittered 2 sample clocks (of adclk) after write into the nco_div_delay register (see note 10) 0 03 0 fd jitter after 3 to 253 sample clocks (all individual values are valid) 1 1 1 1 1 1 1 0 0 fe jitter after 254 sample clocks 1 1 1 1 1 1 1 1 0 ff jitter after 255 sample clocks notes: 9. the formula to convert ncdly[7:0] to delay is straightforward. delay (number of adclk periods) = ndclk[7:0] (except for 0 and 1). 10. adclka/d converter sampling clock caution: this register is also the only means of communicating to the codec that the adclk must be jittered. thus not writing a value implies that jitter will not take place even if other registers have non-default values. as a side consequence, this register does not remember its value. all the others store them unless reset. writing 0 or 1 is not recommended examples: 1. ncdef[7:0] = 64 (dec.), ncdel[4:0] = 1, ncrpt[2:0] = 2, ncdly[7:0] = 5. this shows a default division value of 64, giving a normal adclk of 2.208 mhz (assuming 35.328 mhz input); the division ratio will be 64 + 1 = 65 to effect the jitter, that is, pulling in the clock phase. the jitter will be repeated for 2 consecutive samples. the jitter will take effect 5 adclk sample periods after writing to ncdly. 2. ncdef[7:0] = 63 (decimal), ncdel[4:0] = 1, ncrpt[2:0] = 2, ncdly[7:0] = 5. similar to 1. the default frequency is slightly less than 2.208 mhz. since the division ratio is 63 1 = 62, the clock phase is pushed out. 3. ncdef[7:0] = 64 (decimal), ncdel[4:0] = 0, ncrpt[2:0] = 2, ncdly[7:0] = 5. here the jitter will not be observed, since the delta register is zero. 4. ncdef[7:0] = 64 (decimal), ncdel[4:0] = 1, ncrpt[2:0] = 0, ncdly[7:0] = 5. here the jitter will not be observed, since the repeat register is zero. 5. ncdef[7:0] = 64 (decimal), ncdel[4:0] = 1, ncrpt[2:0] = 2, ncdly[7:0] = 0. this is invalid and not recommended. ncdly[7:0] can not be 0 or 1. 6. ncdef[7:0] = 64 (decimal), ncdel[4:0] = 1, ncrpt[2:0] = 2. here the jitter will not occur since there was not writing to ncdly. the other registers will retain their values as in all other cases.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 25 post office box 655303 ? dallas, texas 75265 nco_delta numerically controlled oscillator delta value register address: 01110b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 ncdel[3] ncdel[2] ncdel[1] ncdel[0] ncrpt[3] ncrpt[2] ncrpt[1] ncrpt[0] table 13. nco_delta delta and repeat d7 d6 d5 d4 d3 d2 d1 d0 hex value bit name description 0 0 0 0 0 00 delta = 0 0 0 0 1 0 08 delta = 1 0 0 1 0 0 10 delta = 2 0 0 1 1 0 18 delta = 3 0 1 0 0 0 20 delta = 4 0 1 0 1 0 28 delta = 5 0 1 1 0 0 30 delta = 6 0 1 1 1 0 38 ncdel[3:0] delta = 7 1 0 0 0 0 40 ncdel[3 : 0] delta = 8 1 0 0 1 0 48 delta = 7 1 0 1 0 0 50 delta = 6 1 0 1 1 0 58 delta = 5 1 1 0 0 0 60 delta = 4 1 1 0 1 0 68 delta = 3 1 1 1 0 0 70 delta = 2 1 1 1 1 0 78 delta = 1 0 0 0 0 0 00 repeat = 0 (same as delta = 0) 0 0 0 1 0 01 repeat =1 0 0 1 0 0 02 repeat =2 0 0 1 1 0 03 repeat =3 0 1 0 0 0 04 repeat =4 0 1 0 1 0 05 repeat =5 0 1 1 0 0 06 repeat =6 0 1 1 1 0 07 ncrpt[3:0] repeat =7 1 0 0 0 0 08 ncrpt[3 : 0] repeat =8 1 0 0 1 0 09 repeat =9 1 0 1 0 0 0a repeat =10 1 0 1 1 0 0b repeat =11 1 1 0 0 0 0c repeat =12 1 1 0 1 0 0d repeat =13 1 1 1 0 0 0e repeat =14 1 1 1 1 0 0f repeat =15
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 26 post office box 655303 ? dallas, texas 75265 mcr master control register address: 01111b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 gp12en dlben alben swrst vcdacpd rxpd txpd swrefpd table 14. mcr control d7 d6 d5 d4 d3 d2 d1 d0 reg value bit name description 0 gp12en no effect on sdx 1 0x80 gp12en show gpio 1 and 2 in sdx primary. 0 dlben no effect on digital loop back 1 0x40 dlben enable digital loop back 0 alben no effect on analog loop back 1 0x20 alben enable analog loop back 0 swrst no effect on reset 1 0x10 swrst perform soft reset 0 vcdacpd power up vcxodac 1 0x08 vcdacpd power down vcxodac 0 rxpd power up rx channel 1 0x04 rxpd power down rx channel 0 txpd power up tx channel 1 0x02 txpd power down tx channel 0 swrefpd power up (soft) main reference 1 0x01 swrefpd power down (soft) main reference notes: 11. the swrst and swrefpd refer to the word software, since the reset is done by register programming as opposed to hard r esets done by forcing pin logic levels. 12. analog loop-back means looping back of the analog tx output to the rx input. this way the codec can be tested without need o f external analog sources. 13. digital loop-back means looping back the digital rx output to the tx input. here we can test the code without the need for a dsp and serial data transfer. caution: all power downs of vcxodac, rx, and tx channels occur with the reference still on. dpll detailed description the default value of register nco_def is 64. with the 35.328 mhz input clock, the output frequency of the pll is 4 35.328 = 141.312 mhz. to obtain an adc clock of 2.208 mhz the divide ratio (controlled by register nco_def) needs to be 64. increasing or decreasing this ratio (for example, 65 or 63) can effect a temporary phase shift. the ratio is controlled by the dsp through register programming. in dpll mode, the adc clock (adclk) will work at 2.208 mhz instead of the 4.416 mhz used in the vcxo mode. the dac clock (daclk) will continue to work at 4.416 mhz. when the adclk is jittered, the daclk is also jittered.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 27 post office box 655303 ? dallas, texas 75265 dpll detailed description (continued) pll (x4) mclkin/ pllclkin nco_def nco_div_delay clock to converter nco_delta [7:4] nco_delta [3:0] + figure 7. dpll internal function block diagram example: assume mclkin/pllclkin=35.328 mhz. when nco_def is programmed as 64, a 2.208 mhz clock is provided to the adc converter according to the following formula: 35.328 4/64 = 2.208 if nco_delta [7:4] is set to 1, nco_delta [3:0] is set to 3, and nco_div_delay is set to 2 (nco_div_delay should be the last register to be programmed), register nco_def will change to 63,63,63,64 at the beginning of the third sampling period. each number (63 or 64) only last one clock (2.208 mhz) cycle. and the combination 63,63,63,64 occurs only once. reprogramming of register nco_div_delay is needed if further adjustment is required. figure 7 shows the timing of sclk with the following setting: nco_delta [7:4] = 1 (delta) nco_delta [3:0] = 1 (repeat) nco_div_delay = 2 (delay) also note that in dpll mode, the adc clock will work at 2.208 mhz, 2 times oversampled, (instead of 4.416 mhz used in the vcxo mode) and the dac clock will continue to work at 4.416 mhz. 16 sclks 16 sclks 16 sclks 16 sclks 21 ns 16/35.328 mhz 16/35.328 mhz 16/35.328 mhz 16/35.328 mhz+1/(4*35.328 mhz) nco_div_delay is programmed by dsp start counting 2 adclk over jitter is done sclk adclk 21 ns 1 adclk over figure 8. adclk jitter example
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 28 post office box 655303 ? dallas, texas 75265 dpll detailed description (continued) to prevent variation in the serial clock width (sclk) due to jitter, the serial clock is modified to have a fixed high level of 14 ns and a low level of 7 ns, thus resulting in a period of 21 ns. the average clock frequency is still 35.328 mhz. after the 16 sclks are complete, the clock goes quiet (no toggle zone) until the rising edge of the next adclk. the length of the no-toggle zone varies with the adclk. figure 9 illustrates an example. sclk 35.328 mhz adclk 2.208 mhz daclk 4.416 mhz 14 ns 7 ns 1/35.328 mhz figure 9. relation of sclk with adclk/daclk in dpll mode absolute maximum ratings over operating free-air temperature (unless otherwise noted) 2 supply voltage, avdd to agnd, dvdd to dgnd 0.3 v to 4.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog input voltage range to agnd 0.3 v to avdd+0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range 0.3 v to dvdd+0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating virtual junction temperature range, t j 40 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t str 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 250 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions power supply min nom max unit su pp ly voltage avdd_rx, avdd_tx, avdd_ref 3 3.3 3.6 v s u ppl y v oltage dvdd, dvdd_io, dvdd_rx 3 3.3 3.6 v digital inputs min nom max unit high-level input voltage, v ih digital p ower su pp ly=33v 2.4 v low-level input voltage, v il digital po w er s u ppl y = 3 . 3 v 0.6 v analog input min nom max unit analog in p ut signal range avdd_rx = 3.3 v, the input signal is measured single ended. avdd_rx/2 0.75 v analog inp u t signal range avdd_rx = 3.3 v, the input signal is measured differentially. 3 vp-p
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 29 post office box 655303 ? dallas, texas 75265 recommended operating conditions (continued) clock min nom max unit input clock frequency 35.328 mhz input clock duty cycle 50% electrical characteristics over recommended operating free-air temperature range, f mclkin = 35.328 mhz, avdd_rx/avdd_tx/avdd_ref = 3.3 v, dvdd = dvdd_io = dvdd_rx = 3.3 v, (unless otherwise noted) tx channel (measured differentially) parameter test conditions min typ max unit gain error 1.5 1.5 db paa step gain error 0.25 db dc offset 50 100 mv cross-talk rx to tx channel 70 db idle channel noise 65 m vrms group delay 30 m s power supply rejection ratio (psrr) 200 mvp-p at 75 khz 70 db analog output voltage load = 2000 w 3 vp-p ac performance snr signal-to-noise ratio 70 db thd total harmonic distortion ratio 70 khz at 1 db (see note 14) 75 db tsnr signal-to-noise + harmonic distortion ratio 68 db 30.1875 khz 71 mt missing-tone test (see note 15) 81.9375 khz 71 db 129.375 khz 71 channel frequency response (refer to figure 13) 30 khz 1.5 1.5 filter gain relative to gain at 77.625 khz pass-band (ripple) 1 1 db 180 khz 70 notes: 14. the input signal is the digital equivalent of a sine wave (digital full scale = 0 db). the normal differential output with this input condition is 3 v pp . 15. 27 tones, 25.875 to 138 khz, 4.3125 khz/step, 0 db reference outputs min nom max unit refp 2.2 2.5 2.8 v refm 0.3 0.5 0.7 v txbandgap avdd_ref = 3.3 v 1.4 1.5 1.6 v rxbandgap 1.4 1.5 1.6 v vmid_rx 1.5 v digital outputs min nom max unit v oh high-level output voltage i oh = 2 ma 2.4 v v ol low-level output voltage i ol = 2 ma 0.6 v
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 30 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, f mclkin = 35.328 mhz, avdd_rx/avdd_tx/avdd_ref = 3.3 v, dvdd = dvdd_io = dvdd_rx = 3.3 v, (unless otherwise noted) (continued) rx channel (measured differentially) parameter test conditions min typ max unit gain error 1.5 1.5 db pga 1 (0 to 12 db in 3-db steps) 1 pga step gain error pga 2 (0 to 18 db in 6-db steps) 1 db pga 3 (0 to 9 db in 0.25-db steps) 0.15 dc offset 50 100 mv cross-talk tx to rx channel 55 db group delay 25 m s idle-channel noise 100 m vrms common-mode rejection ratio (cmrr) 70 db power supply rejection ratio (psrr) 200 mvp-p at 75 khz 70 db analog input self-bias dc voltage 1.5 v rxinp/m 7 k w input impedance hpf1inp/m 70 pf hpf2inp/m 70 pf ac performance snr signal-to-noise ratio 72 thd total harmonic distortion ratio 270 khz at 1 db (see note 16) 82 db tsnr signal-to-noise + harmonic distortion ratio 72 163.875 khz 57 mt missing-tone test (see note 17) 301.875 khz 57 db 508.875 khz 57 channel frequency response (eq[2:0] = 0 db/mhz) (refer to figures 15 and 16) 180 khz 1.5 1.5 filter gain relative to gain at 276 khz pass-band (ripple) 1 1 db 800 khz 25 notes: 16. the analog input test signal is a sine wave with 0 db = 3 vp-p as the reference level. 17. 123 tones, 25.875 khz to 552 khz, 4.3125 khz/step, 6 db.
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 31 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range, f mclkin = 35.328 mhz, avdd_rx/avdd_tx/avdd_ref = 3.3 v, dvdd = dvdd_io = dvdd_rx = 3.3 v, (unless otherwise noted) (continued) vcxo dac parameter test conditions min typ max unit resolution 12 bits dnl differential nonlinearity 1 lsb inl integral nonlinearity 4 lsb monotonicity 12 bits channel gain error db offset error 100 100 mv analog output full scale output voltage load = 50 k w, v dd = 3.3 v 3 v output load 50 k w power dissipation min typ max unit active mode 700 850 mw hardware power down 50 100 mw power dissipation power down mode tx only po w er - do w n mode software power down rx only mw tx + rx + reference
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 32 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) serial port (see figures 7 and 8) and dgpo (see figure 9) parameter min typ max unit t c1 period, sclk 28.3 ns t d1 delay time, fsr high before sclk 7 ns t d2 delay time, fsr high after sclk 7 ns t d3 delay time, fsx high before sclk 7 ns t d4 delay time, fsx high after sclk 7 ns t d5 delay time, sdx data valid after sclk 7 ns t d6 delay time, gpio becomes valid after data is sent 7 ns t f falling time, sclk change from high to low 4.4 ns t h1 hold time, sdr keep valid after sclk 2 ns t r rising time, sclk change from low to high 4.6 ns t su1 setup time, sdr valid before sclk 6 ns t c1 t r t f t d1 t d2 t su1 t h1 d15 d14 d13 d12 d11 sclk (output) fsr (output) sdr (input) figure 10. data transfers from dsp to TLFD500PN sclk (output) fsx (output) sdx (output) t d3 t d4 t d5 figure 11. data transfers from TLFD500PN to dsp
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 33 post office box 655303 ? dallas, texas 75265 valid data t d6 = 7 ns sclk gpio figure 12. gpio bit-to-pin update timing 150 200 0 0.2 0.4 0.6 gain db 100 0 f frequency mhz transmit channel response 50 0.8 1 50 figure 13. transfer characteristic of the transmit filters (complies with itu g.992.2 psd requirement)
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 34 post office box 655303 ? dallas, texas 75265 150 200 0 0.2 0.4 0.6 gain db 100 0 f frequency mhz transmit channel response with hp filter bypassed 50 0.8 1 50 figure 14. transfer characteristic of the transmit filters with hp filter bypassed (complies with itu g.992.2 psd requirement) 100 140 0 0.2 0.4 0.6 0.8 1 gain db 80 60 f frequency mhz receive channel response with different equalizer settings 20 1.2 1.4 1.6 20 0 40 120 460 180 figure 15. transfer characteristic of the receive filters (including out of band 01.6 mhz) (complies with itu g.992.2 psd requirement)
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 35 post office box 655303 ? dallas, texas 75265 30 40 0 0.2 0.3 0.4 gain db 20 10 f frequency mhz receive channel response with different equalizer settings 0 0.5 0.6 20 10 50 60 0.1 figure 16. transfer characteristic of the receive filters (in-band 00.6 mhz) (complies with itu g.992.2 psd requirement)
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 36 post office box 655303 ? dallas, texas 75265 application information output signal 5 txoup dvdd 31, 39 0.1 m f vcxocntl 13 reset 38 pwrdn 17 pllsel 42 mclkin/pllclkin 37 gpio0-gpio7 23-30 dgpo 35 input signal need to have avdd_rx/2 common mode voltage dvdd_rx 51 dvdd_io 18 vss 80 avss_ref 44 avss_tx 8 avss_rx 49 avss_rx 69 analog ground avdd_ref 47 avdd_rx 48 avdd_rx 68 avdd_tx 7 analog power supply 10 m f 1.0 m f 1.0 m f analog power supply analog ground 6 txoum 70 rxinp 71 rxinm 75 hpf2outm 72 hpf2outp 74 hpf2inp 79 hpf1outm 76 hpf1outp 77 hpf1inm 78 hpf1inp 73 hpf2inm external clock to vcxo 10 m f 10 m f 10 m f 10 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 16 compdac1 15 compdac2 50 v mid_rx 14 txbandgap 43 rxbandgap 45 refm 46 refp TLFD500PN digital power supply dvss 34,40,41 dvss_io 33 dvss_rx 52,54,57 digital ground fsx 22 fsr 21 sdr 20 sclk 19 sdx 18 digital interface to dsp figure 17. typical application circuit
TLFD500PN 3.3 v integrated g.lite analog front end slas207a june 1999 revised november 1999 37 post office box 655303 ? dallas, texas 75265 mechanical data pn (s-pqfp-g80) plastic quad flatpack 4040135 / b 11/96 0,17 0,27 0,13 nom 40 21 0,25 0,45 0,75 0,05 min seating plane gage plane 41 60 61 80 20 sq sq 1 13,80 14,20 12,20 9,50 typ 11,80 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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